Location:
Search - clock algorithm
Search list
Description: ＳＴＭ３２具有３２位秒计数器，可以通过一定算法实现实时时钟功能，例子提供这种算法-STM32 with 32 seconds counter, through a certain algorithm can realize real-time clock function, for example, the provision of such algorithm
Platform: |
Size: 3072 |
Author: wdzjj |
Hits:
Description: 数字钟的单片机实现，有详细的源码及解释
算法结构清晰，对单片机学习者非常有用
对于电子专业的，拿来当课程设计也是相当不错的
功能有：
1，完成秒／分／时的依次显示并正确计数；
2，秒／分／时各段个位满10正确进位，秒／分能做到满60向前进位；
3，定时闹钟：实现整点报时，有扬声器发出报时声音；
4，时间设置，也就是手动调时功能：当认为时钟不准确时，可以分别对分／时钟进行调整；
5，可以清零；完成暂停；可以随时记时、暂停后记录数据。-The single-chip digital clock realized, a detailed algorithm for the structure of source code and explanations clear, very useful for learners Singlechip electronic professional, used as the curriculum design is quite nice features are: 1, completed sec/min/h and the sequence shows the correct count 2, seconds/minutes/hours in the paragraphs of 10 bits into the correct place, seconds/minutes to achieve the age of 60 to the forward position 3, regular alarm clock: to bring the whole point of time, there are loud speakers voice time 4, time settings, which is manually adjusted when the function: When that clock is inaccurate, you can separately sub/clock adjustment 5, can be cleared the completion of the suspension can always remember when suspended after the record data .
Platform: |
Size: 26624 |
Author: 何强 |
Hits:
Description: 关于多工能数字时钟的年月日及闰年和平年的算法-On the multi-tasking digital clock date and the leap year algorithm Year of Peace
Platform: |
Size: 3072 |
Author: me |
Hits:
Description: 1、学习Proteus的使用，
2、学习并掌握编译器Keil C环境下做51的系统开发
3、进一步学习时钟的算法，会使用硬件实现此算法；
4、了解基于RTOS上的多任务分时使用CPU，掌握任务的创建、删除、等待以及任务之间的同步等基本的多任务程序设计方法、掌握操作系统的基本原理。
-1, to learn the use of Proteus, 2, to learn and master the Keil C compiler environment do 51 System Development 3, further study clock algorithms, will use the hardware to achieve this algorithm 4, understanding RTOS based on the time-sharing the use of multi-tasking CPU, have the task to create, delete, waiting, as well as the synchronization between the mandates of the basic procedures for multi-tasking design method, grasp the basic principles of the operating system.
Platform: |
Size: 55296 |
Author: bluefeifei |
Hits:
Description: 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Platform: |
Size: 23552 |
Author: charity |
Hits:
Description: Verilog 下 16位除法算法程序，高精度，固定17个时钟周期-Verilog under 16 division algorithm procedures, high-precision, fixed in 17 clock cycles
Platform: |
Size: 146432 |
Author: huangyongbing |
Hits:
Description: 采用51系列单片机为控制核心，包括电源变换处理及分配模块，恒流源模块，单片机主控模块，键盘输入模块，LCD显示模块，数模/模数转换模块，语音模块和实时时钟模块的9个部分。通过键盘设定好需要输出的电流值后，单片机对设定值按照一定的算法进行处理，经数模输出电压控制恒流源电路输出相应的电流值-51 Series single-chip microcomputer used for the control of the core, including the processing and distribution of power transform module, constant current source module, single-chip control module, the keyboard input module, LCD display module, digital-to-analog/analog-digital conversion module, voice module and real-time Clock Module Part 9. Through the keyboard need to set output current value, single-chip microcomputer according to the settings of the algorithm processing, digital-to-analog output voltage by the control constant current source circuit output current value of the corresponding
Platform: |
Size: 169984 |
Author: cwyctz |
Hits:
Description: 该代码是从SPEEX中提取出来有关回声消息部分的源码
它采取的是在频域进行操作，效果比较好"
经测试，如果原始声音与用于回声消息的参考声音之间存在时钟不同步时，极易发生在回音消息算法中的反溃发散现象.
压缩包中含有测试语音文件：
Input_exsample_stereo.pcm: 8k16bit的线性pcm，含双通道语音。
vleft.pcm: 8k16bit linear pcm, 从Input_exsample_stereo.pcm 中分离出来的左声道音频。
right.pcm: 8k16bit linear pcm, 从Input_exsample_stereo.pcm 中分离出来的右声道音频。
-The code is extracted from the SPEEX news out of the echo part of the source it is taken to operate in the frequency domain, the effect is better " by the test, if the original voice message and a reference for the echo between the voice of the clock is not synchronized easily occurred in the response message algorithm in the phenomenon of anti-ulcer divergence. compressed package file containing the test voice: Input_exsample_stereo.pcm: 8k16bit linear pcm, including dual-channel voice. vleft.pcm: 8k16bit linear pcm, from Input_exsample_stereo.pcm separate the left channel audio. right.pcm: 8k16bit linear pcm, separated from the Input_exsample_stereo.pcm the right-channel audio.
Platform: |
Size: 936960 |
Author: wlch |
Hits:
Description: 支持多道程序的进程控制模块的设计与实现，要求完成以下功能：
1，进程控制：创建、撤销、阻塞、唤醒
2，进程调度：CPU调度算法
3，进程同步：信号量的定义、信号量的操作（wait、signal）
4，内存管理：实现页式内存管理、LRU页面置换
5，中断处理：中断响应、中断处理
6，时钟管理：时钟、定时器
7，用图形化方式展示多进程并发执行过程 -Support the process of multi-channel process control module of the Design and Implementation, required to complete the following functions: 1, process control: the creation, revocation, blocking, wake-up 2, the process of scheduling: CPU scheduling algorithm 3, the process of synchronization: the definition of semaphores, semaphore operation (wait, signal) 4, memory management: memory management to achieve page, LRU replacement page 5, interrupt handling: interrupt response, interrupt handling 6, clock management: clock, timer 7, a graphical display with multi-process concurrency the implementation process
Platform: |
Size: 1977344 |
Author: yefeng |
Hits:
Description: 二进制时钟，没用什么算法，只是实现功能而己，有知道算法的给个给小弟。kevinmitnice@gmail.com-Binary clock, what algorithm is useless, but the realization of their own functions, there are know to the algorithm to a boy. kevinmitnice@gmail.com
Platform: |
Size: 7168 |
Author: 龙啸 |
Hits:
Description: 12864液晶计数器 带日期算法 时钟显示 -12864 Counter LCD display clock with date algorithm
Platform: |
Size: 109568 |
Author: Kevin |
Hits:
Description: 昨天晚上一直都是在郁闷彷徨中度过，越是心烦越是看不懂，随之而来的，是我无穷无尽的抱怨，像个小怨妇似的，呵呵，今天早上起来，心情还不错，本想读读英语呢，因为我发现还得参加研究生学位英语考试，我的英语都荒废一年了~~吼吼..应该还能捡的起来的~~可是不知怎么滴，想起了那个微分方程的作业..打靶法，就开始跟它较劲了，难，是吧，我还偏要做出来~~大早上八点就开电脑，一边编程一边看理论知识，从一点点的算法到一步步的程序~~直到十点，才搞定，好开心哦~~可是昨天晚上被这个算法折磨的很惨~~
也许我的性格中有一种不服输的因子存在吧....虽然很多时候，我对周围的一切波澜无惊~~是比较淡漠...
说了n次的想抄别人的作业，想了n次的要放弃~~可是，我怎么也行动不起来（懒的行动）~~
华东理工大学出版社，微分方程数值解法，69页，7.（2）题，取h=0.05.并且老师要求隔4个输出一个。
-Last night has been spent in the depressed anxious, the more upset the more we can not read, followed by one of my endless complaining, like a small怨妇like, huh, huh, this morning, the mood was also Yes, this would like to read English, because I found that post-graduate degree have to take part in examinations in English, my English has abandoned a year ~ ~吼吼.. should be able to pick up the ~ ~ but do not know how to drop, think of the The differential operation .. shooting method, with its war began, and difficult, is not it, I want to do it all out ~ ~ 8:00 am on opening large computers, while watching the theoretical side of programming knowledge, from a little bit of algorithm to a step-by-step process ~ ~ until 10 o clock before we get so happy oh ~ ~ But last night was miserable this algorithm torture ~ ~
Perhaps I have the personality factor of the existence of an unwillingness to admit defeat .... although it very often, I am all the waves around without fear ~ ~ is relativ
Platform: |
Size: 2048 |
Author: 毛东 |
Hits:
Description: 时钟便面设计代码，主要针对多个时钟的不同界面风格和一致的时针和分针的走时，并提供详细算法-Clock face design code will be mainly targeted at a number of different clock style and consistent interface clock and the minute hand of the travel time and provide a detailed algorithm
Platform: |
Size: 4508672 |
Author: xiao_yin_ying |
Hits:
Description: 潘明海 刘英哲 于维双 (论文)
中文摘要：
本文讨论了一种可在FPGA上实现的FFT结构。该结构采用基于流水线结构和快速并行乘法器的蝶形处理器。乘法器采用改进的Booth算法，简化了部分积符号扩展，使用Wallace树结构和4-2压缩器对部分积归约。以8点复点FFT为实例设计相应的控制电路。使用VHDL语言完成设计，并综合到FPGA中。从综合的结果看该结构可在XC4025E-2上以52MHz的时钟高速运行。在此基础上易于扩展为大点数FFT运算结构。
-Pan Minghai Liuying Zhe Yu-dimensional pairs (thesis) Chinese Abstract: This paper discusses an FPGA can be implemented on the structure of the FFT. The architecture based on pipeline architecture and fast parallel multiplier butterfly processor. Multiplier using modified Booth algorithm simplifying the partial product sign extension, use the Wallace tree and 4-2 compressor for partial product reduction. 8-point complex-point FFT as an example design of the corresponding control circuit. To complete the design using the VHDL language, and integrated into the FPGA. From the results of a comprehensive look at the structure can be XC4025E-2 with 52MHz clock on the high-speed operation. On this basis, easy to expand the structure for large point FFT operations.
Platform: |
Size: 128000 |
Author: culun |
Hits:
Description: 单摆实时仿真软件是利用混合语言编程方法实现的实时仿真软件，仿真算法是四阶龙格库塔法，定时器使用与PC兼容的8253中的0通道，实时主要利用了与PC兼容的主片8259A中IR0的日时钟中断，使用BC3.0进行混合语言编译，产生的代码存放路径必须有EGAVGA.BGI图形驱动程序，该程序具有简单的人机交互界面，适合研究生计算机仿真课程的教学使用。-Real-time simulation software is a simple pendulum using mixed-language programming to achieve real-time simulation software, simulation algorithm is fourth-order Runge-Kutta method, using the PC-compatible timer 8253 in the 0-channel, real-time mainly use the PC-compatible with the main 8259A chip clock in the day IR0 interrupt, the use of BC3.0 mixed language compiler to generate code that stored the path must have EGAVGA.BGI graphics drivers, the program has a simple interactive interface, suitable for post-graduate courses teaching the use of computer simulation .
Platform: |
Size: 13312 |
Author: 赵文龙 |
Hits:
Description: jogl（java绑定opengl）源码，此文件包括opengl的直线、圆以及三角形篓垫算法，其中的直线和圆组成一个时钟。-jogl (java binding opengl) source, this document includes opengl linear, circular and triangular baskets, mats algorithm, which form a line and round the clock.
Platform: |
Size: 11992064 |
Author: luolei |
Hits:
Description: 用Gardner算法时钟同步的BPSK的源程序-Gardner algorithm for clock synchronization with the source code BPSK
Platform: |
Size: 1024 |
Author: 戴十三 |
Hits:
Description: 在数字系统中，一般存在多个芯片，利用不同的特点用于实现不同的功能，一般都包含CPU,FPGA,AD,DA,memory，ASSP（专用标准模块）,ASIC等。CPU用于进行智能控制，FPGA进行硬件算法处理和多设备接口，AD进行模数转换，DA进行数模转换，memory存储临时数据。因此，FPGA如何与其他芯片进行通讯是重要的设计内容。数据输入，数据输出，双向通讯，指令传递，地址管理，不同时钟的异步通讯问题等等都需要处理。最基本的MEMORY如SRAM(128KX8bbit静态存储器628128)涉及到其中的输入，输出，双向通讯，地址管理问题，具有很强的代表性。在同步数字系统中更大量用到FIFO,SDRAM等等。其中FIFO使用方便简单，用处很广。在QUARTUSII软件库中，就有各种FPGA片内MEMORY供使用。但是FPGA的片内MEMORY容量太有限，因此外部MEMORY也是经常需要的。因此，本程序让大家学习控制芯片内外的MEMORY,为与其他智能设备的通讯学习打下基础。-In the digital system, generally there are several chips, the use of different features used to implement different functions, generally includes CPU, FPGA, AD, DA, memory, ASSP (application specific standard module), ASIC and so on. CPU is used for intelligent control, FPGA hardware algorithm processing and multi-device interface, AD to ADC, DA for digital-analog conversion, memory to store temporary data. Therefore, FPGA how to communicate with other chips are important design elements. Data input, data output, two-way communication, instruction delivery, address management, different clock asynchronous communication problems, and so have to deal with. If the most basic MEMORY SRAM (128KX8bbit static memory 628 128) which involved the input, output, bi-directional communication, address management issues, with strong representation. In synchronous digital systems a lot more use FIFO, SDRAM, etc.. One simple and easy to use FIFO, use very broad. In QUARTUSII software library, there ar
Platform: |
Size: 223232 |
Author: 平凡 |
Hits:
Description: OQPSK信号的相位估计，用的是相位与时钟联合估计算法，适用于突发的卫星信号等-OQPSK signal phase estimation, using a phase estimation algorithm combined with the clock for emergency satellite signals
Platform: |
Size: 2048 |
Author: wangsha |
Hits:
Description: OQPSK信号的频率估计，用的是相位与时钟联合估计算法，适用于突发的卫星信号等-OQPSK signal frequency estimation, using a phase estimation algorithm combined with the clock for emergency satellite signals
Platform: |
Size: 2048 |
Author: wangsha |
Hits: